Presently, a memory device such as, for example, a phase change memory (PCM) device may use a higher potential path (e.g., bit-line path) of alternative paths (e.g., bit-line path or word-line path) to carry out read (e.g., sense) and/or write operations (e.g., set or reset). Generally, a selection operation is performed to select a memory cell of the memory device that is to receive the read/write operations. Such current memory device configurations may present a variety of challenges. For example, high displacement currents through a memory cell during read/write operations may disturb or damage the memory cell. Further, a challenge may arise when transitioning from the selection phase to the read/write operation. The transition may impose critical timing requirements to prevent damage to the selected memory cell or to maintain a selected state of the memory cell. Another challenge may include a delay in resolving a signal during the read/write operation when the higher potential path has a relatively larger capacitance than an alternative path. The delay may adversely affect throughput or speed of the read/write operation. Furthermore, circuitry that performs read and/or write operations may operate at relatively higher voltages when coupled to the higher potential path, which may result in the read/write circuitry operating at slower speeds and consuming larger area of the memory device. The above challenges may constrain a maximum tile size of the memory device and require the use of more complex and/or costly semiconductor fabrication technology to fabricate smaller tiles.